An example of a conventional transmission frame format converter circuit with a FIFO memory is shown in FIG. 1.
As shown in FIG. 1, the data-writing side of FIFO 110 in the transmission frame format converter circuit comprises a serial-to-parallel(S/P) converter 101, a N-divided frequency generator 108. a writing counter 102, and a writing clock generator 108.
The S/P converter 101 converts write-in data which is input in the form of serial data 103 into parallel data 106, according to a divided frequency clock, which is explained later, to be output from the writing counter 102, and then outputs it to FIFO 110. The N-divided frequency generator 121, to which an extraction clock 105 from a transmission line is input, outputs a N-divided clock 120.
The writing counter 102, to which a frame pulse 104 and the N-divided frequency clock 120 from the N-divided frequency generator 121 are input, outputs a write-side divided frequency clock 107. The divided frequency clock 107 output from the writing counter 102 is supplied to the S/P converter 101 and the writing clock generator 108. The writing clock generator 108, to which the divided frequency clock 107 is input, outputs a write clock 109 for writing in FIFO 110.
The parallel data 106 which are converted by and output from the S/P converter 101 are written in FIFO 110 according to the writing clock 109 output from the writing clock generator 108.
The data-reading side of FIFO 110 in the transmission frame format converter circuit comprises a M-divided frequency generator 122, a reading counter 116, a reading clock generator 114, and a parallel-to-serial(P/S) converter 115.
The M-divided frequency generator 122, to which the extraction clock 105 from the transmission line is input, outputs a M-divided frequency clock 119, where M is not the same value as N and satisfies the relation of M&gt;N or M&lt;N. The reading counter 116, to which the M-divided frequency clock 119 and a framepulse 118 are input, outputs a read-side divided frequency clock 113, which is supplied to the reading clock generator 114 and the P/S converter 115. The reading clock generator 114 outputs a read clock 111 for reading data from FIFO 110 according to the divided frequency clock 113 to be input.
Data to be read out from FIFO 110 according to the read clock 111 are converted into serial data 117, which are output as read-out data.
However, in the conventional transmission frame format converter circuit, the read clock forces data to be read out regardless of the state that the data is not yet written in FIFO since the writing and reading operations are conducted independently of each other. Thus, data to be forcibly read out from FIFO must be acknowledged as effective data and transmitted even if the data are meaningless or useless.